1. Field of the Invention
The present invention relates to semiconductor devices, and, more particularly, to forming multisegment "superchips", employing coplanar integration of a plurality of individual segments, each segment having formed thereon various circuits and circuit elements.
2. Description of the Related Art
Although the cost of designing increasingly complex integrated circuit (IC) devices continues to drop such that extremely complex products can now be designed on a desktop workstation, the cost of manufacturing these devices as measured by the required investment in capital equipment and ultra-clean rooms is rising at an astronomical pace. The continued decreases in circuit feature-size and simultaneous increases in chip size in order to get more functional capability on each chip is making it extremely difficult to maintain profitable yields. The Poisson yield model Y=exp(-DA), where Y is fractional yield, D is the net fatal defect density per unit area, and A is the chip area, gives a reasonably good fit to the behavior of yield as a function of those two parameters. Since this is an exponential relationship, one can see that any increase in either chip area A or defect density D has severe negative yield and profitability impact. Profitability is hurt because the cost of processing a wafer of chips is constant regardless of how many chips are good or bad.
The net fatal defect density, usually expressed in terms of fatal defects/cm.sup.2 of chip area, takes a dramatic upturn as the size of a chip's features are reduced unless extraordinary measures are taken to reduce the source of such defects. In general, a fatal defect would typically be caused by a particulate whose size is some fatal fraction of the smallest feature size found on the chip. As examples, a state-of-the-art chip may have 0.8 .mu.m spaces between its metallic interconnects. Those closely spaced interconnects can certainly be shorted by a 0.8 .mu.m particle or by an agglomeration of smaller particles situating themselves in the narrow spaces. The same chip may have a 200.ANG. or 150.ANG. gate oxide whose growth can certainly be interfered with by the presence of a contaminant whose size is on the same order of magnitude as the oxide thickness, i.e. 150.ANG.. In fact, a few monolayers of contaminant can cause problems. Thus, enormously expensive ongoing measures are required just to maintain constant defect density D, let alone decrease D, as features get smaller. The number of competitors able to afford the investments required to do this is rapidly dwindling, while the remaining manufacturers increasingly seek government funding to help in this undertaking. Countries not having this ability are in strategic trouble.
As mentioned above, the defect density will rise drastically with circuit feature-size shrinking unless great efforts are made to clean up the manufacturing environment, tools, people, and consumable materials. Other obvious variables which influence defect density are the number of process steps involved and the individual cleanliness of each of those steps as they are integrated together as well as the quality of the monolithic substrate starting-material employed to manufacture the devices. Historically, there has been substantial pressure to simplify process-complexity in order to improve yields. Simplification means using fewer and simpler process steps less prone to defect generation. There has also been substantial resistance to the widespread use of better higher-performance substrate materials such as gallium arsenide because such new materials frequently incorporate more inherent crystalline defects than silicon and are more fragile, which limits yields.
Independent of the concerns about defects and yields are the disadvantages of monolithic chips relative to their process inflexibility. As an example, consider the presently separate silicon chip industry and gallium-arsenide chip industry. Gallium arsenide's strengths are its inherent speed and ability to easily provide either optoelectronic or digital devices at modest levels of integration. Silicon's relative strengths are its slower yet useful speed and its inherently high level of achievable integration due to lower process and substrate defect densities and lower power density.
At present, it is impossible to combine both materials in one monolithic substrate and simultaneously build silicon and gallium arsenide digital circuits along with optoelectronic gallium arsenide devices without resorting to exceedingly complex defect-prone gallium arsenide-on-silicon epitaxial techniques. Such techniques have yet to integrate more than a handful of devices for military purposes where cost is no object. Without using molecular beam and other epitaxial techniques well-known in the art, the goal cannot be reached even for that very simplistic level of integration. It is to be understood that the level of integration possible in such work is many orders of magnitude cruder than in silicon technology wherein one million devices can be commercially integrated today.
Numerous telecommunication and computing applications await the solution to the problem of achieving mixed technology VLSI. In many cases, it would be highly advantageous, in terms of performance, to execute silicon digital designs completely in gallium arsenide, but silicon devices incorporating 100,000 gates or more will have extremely poor yields with the inherently more defectprone gallium arsenide material and processes. Thus, not only cannot one achieve VLSI in mixed technologies, but it is virtually impossible to achieve VLSI in straight gallium arsenide in large million-device chips like those made of silicon today.
The list of attractive products which could be made possible if defect density were not such a dramatic limiter of yield and if one could easily monolithically combine the benefits of presently incompatible or unacceptablycomplex process-technology combinations is endless. In the area of memory devices, one could construct presently unyieldable ultrafast static random access memories (RAMs) of multimegabit density at low cost in gallium arsenide. In the area of sensors, one could construct presently unyieldable silicon charge-coupled device (CCD) imaging chips of several million pixels and thus obtain electronic images of fine photographic quality. In the area of microprocessors, one could obtain supercomputer performance on a single, very large chip incorporating silicon memory and gallium-arsenide logic. Numerous incompatible technologies such as semiconductor gallium-arsenide lasers, optical detectors, superconducting thin films and devices, ferromagnetic nonvolatile memories, combinations of microwave and conventional digital/analog devices, high electron mobility transistors (HEMT), quantum devices, power devices, and bubble memories could each contribute to overall, uncompromised solutions implemented on one chip. An array of present system-level limitations such as chip-to-chip propagation delays, clock skew between devices and reliability and cost disadvantages associated with multichip solutions could be overcome by replacing multiple incompatible chips with one chip.
The closest that existing technology can presently come to the above is with hybrid-circuit techniques. In short, the printed circuit board is replaced with a far smaller ceramic substrate to which the same chips are attached. The ceramic substrate, essentially an ultra-fine-line printed circuit board, permits the chips to be packaged closer together and permits the on-substrate incorporation of passive elements such as laser-trimmed resistors and capacitors. This does improve the performance and reliability relative to a printed circuit board technique, but the cost is extremely high and the performance is still far from that of a single-chip solution. Lately, the trend is toward replacing the ceramic substrate with a silicon substrate which can be manufactured on the same equipment as the chips themselves. Thus, the interconnect linewidths are reduced to about 10 .mu.m for controlled impedance in this more compact implementation, rather than the larger linewidths measured in thousandths of inches (0.001) typical of ceramic substrates. Even in this approach, the interconnections made between the chips and the substrate are far larger in scale than the inherent feature size of the chips themselves. The signals passing between such chips pass out of a microscopic world (on-chip) into a relatively macroscopic world (on-substrate) and then back onto some neighboring chip. Having to deal with the inductance and capacitance discontinuities and and having to optimize the transmission-line behavior of these signal passages results in performance degradations relative to a one-chip solution. Needless to say, the reliability impact of a multichip hybrid approach such as this is also quite negative relatively speaking because in a one-chip solution one does not have to employ chip-to-substrate solder microjoints which are much more unreliable (and much more expensive) than on-chip thin film interconnections.
At present, there is no available method which will permit the manufacture of wafer-scale devices incorporating any desired mix of process technologies. There is not even a manufacturable wafer-scale device limited to one process technology which does not grossly compromise performance due to extensive use of redundancy. The only conceivable approach to currently building a single process logic/memory wafer-scale device would have to incorporate extensive use of redundant backup circuits. The problem with these approaches and other similar discretionary wiring approaches is that the more redundancy one employs to obtain yield, the further one gets from the performance of the most compact implementation, that of a yielding non-redundant device. This is particularly true for logic devices, and since increasingly most application-specific device types employ logic devices, the argument is qualitatively correct in general.
The objective of the presently disclosed invention is to permit chip manufacturers to reduce the impact of the exponential yield law such that they can both yield much larger chips at a given fixed feature size and defect density or conversely build much denser chips (smaller feature size) at a fixed chip size in spite of higher defect density. Likewise, such manufacturers would be able to combine various process and device technologies in any desired manner regardless of their present monolithic incompatibility. The present invention does not eliminate the benefit of defect density reduction; it simply greatly extends the scale and complexity of what is manufacturable at any given fixed defect density.
It must be emphasized that the objective of this invention is not to create an improved higher-density multichip hybrid whereon interchip connections must still pass from chip to substrate to chip and are still of a scale and density considerably below that of the chips themselves and large spaces are necessary between such chips such that they can be mounted, tested, reworked or otherwise individually processed. Rather, the primary objective is to implement all such chips in one chip. This will be done in a manner such that the result is identically physically equivalent to all of the circuitry being monolithically implemented. The strategy is to make the superchip in pieces and put it together. If one makes such a superchip of total area A in N pieces, then the area of each piece, or segment, becomes A/N. Thus, the yield of each of the individual unassembled segments becomes Y.sub.s =exp(-DA/N). The yield of joinging an incremental segment to a superchip being assembled must be high, i.e., nearly unity, and can be assigned on a per incremental segment basis as Y.sub.j. For a superchip containing N segments, the total superchip yield based on the total area of substrate material processed can be written as the product of the unassembled segment yields and the yielded segment-joining operations used to assemble the good segments. Since the first segment is not joined until a second segment is presented for the first joining operation, then the total joining yield is Y.sub.j.sup.N-1. This represents how often one can successfully execute all of the segment joining operations within a given superchip. The total segment yield in the simplest case wherein all N segments are identical is exp(-DA/N). Thus, Y.sub.superchip, just like the yield of today's monolithic devices, is a measure of how much starting material is successfully yielded. Accordingly, the product of the fractional portion of material which yields good unassembled segments and the probability of those good segments being successfully assembled represents the superchip yield as well as the efficiency of yielding the original raw material. ##STR1## The yield improvement due to the segmented approach is simply ##EQU1##
Obviously, for values of DA which are realistic, i.e., at least unity, values of N of only 3 or greater and values of Y.sub.j of 0.95 (i.e. 95%), then the yield improvement by segmentation can be at least 75% (i.e., the ratio is 1.75). For more likely applications, DA would be much larger, say 5 to 10, giving improvements in yield for three segments of from 2500% (ratio=25) to 70,800% (ratio=708). For the same two cases if the number of segments is increased from N=3 to N=6, then the improvements range from 5,000% (ratio=50) to 322,000% (ratio=3,220). Thus, it becomes possible not only to obtain acceptable yields for any size superchip but to freely mix technologies among the segments.
The obvious challenge is how one can possibly hope to align and join such segments in a manufacturing environment in high volume. Just the task of aligning two such segments even in one direction on a submicrometer-accuracy scale is complex and requires exotic micromanipulation devices. What is required is three-dimensional X,Y,Z and .theta. (angle) matchup on N segments simultaneously, and then the implementation of a joining interconnection process on a scale equivalent to that of the device features themselves with very high yields and low built-in stress. Thus, not only is it required to simultaneously mechanically manipulate N segments in three dimensions, but it also is required to do so in an ultra-clean, non-defect-producing manner. This is inconceivable, given present technology, the severe defect restrictions, and the required throughput needs necessary for any commercially successful product.
The only direct attempt to pseudomonolithically build chips from segments known to the present inventor and which claims to result in chips whose assembled segments are essentially indistinguishable from the monolithic approach is that of Biegelsen et al, U.S. Pat. No. 4,542,397. Biegelsen et al partially address only the alignment issue, but not the joining and defect issues.
The approach of Biegelsen et al has four deficiencies, two of which are fatal. The first fatal deficiency is that the invention requires that the wafers employed be of &lt;110&gt; axial orientation semiconductor crystal, a seldom-used orientation not desirable in integrated circuit device manufacturing, wherein &lt;100&gt; material is exclusively used in order to minimize built-in gate oxide charges and carrier mobility anisotropies in silicon devices. The approach of Biegelsen et al will not give vertical chip edges in the &lt;100&gt; material most commonly used. One is limited, even in &lt;110&gt; material, to chip shapes which follow his latent crystal planes.
The second fatal deficiency for the Biegelsen et al approach is that segments such as those defined by Biegelsen et al are ultrafragile in that they consist of brittle semiconductor materials with razor-sharp edges and no methodology is presented which will keep those edges from damaging each other. Even the slightest mechanical contact of two segments with any velocity appreciably above zero will produce particulate debris and edge damage. Such debris will foul the smooth motion and joining alignment required. Such damage and debris will prevent the implementation of submicrometer intersegment interconnections. Although Biegelsen et al suggest employing a grooved surface plate into whose surface such debris can fall, the damage to the integrity of the edges is already done. Furthermore, the active device surface in the approach of Biegelsen et al must be face-up on their vibrating table or it will be damaged. Thus, chip segments of different thickness cannot easily be joined due to their height mismatch.
The debris described above will also cause defects in the later patterning of the intersegment interconnections. It must be emphasized the defects produced by the segments and energetic forceful segment-alignment mechanics described by Biegelsen et al are just the opposite of what chip-manufacturers are spending billions of dollars to attain, i.e., ultra-clean, particulate-free operations with no instances of mechanical abrasion or tribologically-produced debris. Any contact with the product must be highly controlled, reproducible and clean, and preferably not contact the active device surface at all.
Biegelsen et al suggest that their grooved plate will catch the debris, but submicrometer debris is more affected by electrostatic and turbulence effects than it is by gravity. Wafer manufacturers have to use very aggressive cleaning techniques not amenable to such segments to remove such debris from wafers.
Two additional serious deficiencies are (1) the limited segment shapes available and resulting geometric difficulty of simultaneously abutting an array of diamondshaped segments and (2) the fact that Biegelsen et al say nothing in detail about how to interconnect the segments as formed using their technique once they are abutted and only reference one to other patents, such as U.S. Pat. No. 3,870,850 and U.S. Pat. No. 3,301,716, which do not appear to even be remotely applicable to the task. This is hardly a trivial matter, as Biegelsen et al clearly imply. The present invention describes the important issues of gap control and differential expansion not discussed or referred to by Biegelsen et al.
If one has ever taken square pieces of tile and placed them on a flat surface and tried to simultaneously compact them into a large square array with no gaps, one notes how easy it is for even one badly aligned segment to ruin the fit of the entire array. This is especially true for four-sided segments. The only solution is to compact them one at a time, which greatly slows down the process, especially if each one has to be individually manipulated mechanically. Arrays whose segment-edges fall on common lines passing all the way through the superchip will always have this binding problem, especially if the segments are gravitated or shaken and slid together in the manner of Biegelsen et al. The accumulation of tolerances, i.e., segment size variations, can also cause binding problems in such arrays. The approach of Biegelsen et al is not conducive to evenly distributing tolerance variations over the whole array.
Further, the three-dimensional alignment accuracy of the Biegelsen et al approach is limited by the defects produced during the intersegment dry-contacting and drysliding events which takes place numerous uncontrollable times and by the nature of some potentially particulate-laden reference surface on which their segments lie. From the figures of Biegelsen et al, one cannot even conclude whether or not they employ the device-surface to lie against the reference surface (upside down), thus permitting segments of different thickness typical of the thickness variation between wafers but introducing damage directly to the active device surfaces. Their alternative, as mentioned, is to have the segments sit face-up, in which case, any segment thickness variation will not allow the chip edges to match. As noted herein, the defect particles and corresponding edge-damage produced in the Biegelsen et al approach will not only interfere with micrometer-scale alignment due to binding and debris between and under segments, but will also interfere with the later formation of intersegment interconnections because portions of the segment edges are missing on the scale of the interconnects to be implemented (i.e., about one micrometer or less).
References to "closely abutting" integrated-circuitry constructed on multiple independent bodies of semiconductor material are undoubtedly numerous. As an example, U.S. Pat. No. 4,322,737, issued Mar. 30, 1982, to Jack Sliwa and assigned to INTEL Corp. clearly shows such a concept in FIGS. 17a and 21. However, this reference, like so many others, is not specifically designed to implement micrometer-scale intersegment interconnections, so all of the particulate and edge damage issues are ignored and no particular claims relating to micrometer-scale extendability are made.